1. Field of the Invention
The present invention relates to a semiconductor device having a gate electrode formed by a multi-layered structure and a method of making the same.
The present Application is based on Patent Application No. Hei 10-109208 filed in Japan, the content of which is incorporated herein by reference.
2. Background Art
Recently, dual gate electrodes have been used for MOS transistors, that is, N.sup.+ gates have been used for NMOS transistors and P.sup.+ gates have been used for PMOS transistors.
In the case of using the dual gate structure, the following problems are encountered. One problem is that impurities can pass through the gate.
Practically, it is known that boron used as a dopant for the source/drain and the gate electrode passes from the gate electrode to the gate oxide layer and reaches the threshold control region (channel region) as a result of thermal treatment at high temperatures, which results in causing the fluctuations of the threshold value.
This phenomenon is particularly remarkable when the boron is doped using boron fluoride (BF2) by ion implantation.
Another problem is that the gate electrode is subjected to depletion. Actually, arsenic used for doping in the source/drain and the gate electrode is less thermally diffusible in comparison with boron. Thus, if the sufficient thermal treatment is not conducted after ion implantation of arsenic, the concentration of arsenic at the bottom surface of the NMOS-type gate electrode (near the interface with a gate oxide film) becomes low, causing depletion and reduction of the drain current.
The above mentioned two problems are opposite from the technical point of view and cannot be solved only by optimization of the heat treatment.
Moreover, it becomes an important object to improve the reliability of the gate oxide film, because the gate oxide film has become thinner with advances in the microstructure of transistors.
Recently, M. Koba et al. reported in "Improving Gate Oxide Integrity in p+ PMOSFET by Using Large Grain Size Polysilicon Gate" IEDM Tech. Dig., p. 471, 1993, that the initial withstanding voltage can be improved when the gate electrode is formed using large grain polycrystalline silicone.
However, H. Ito et al. reported in "Gate Electrode Microstructure Having Stacked Large-Grain Poly Si with Ultra-Thin SiOx Interlayer for Reliability in Sub-micrometer CMOS" IEDM Tech. Dig., p. 635, 1997, that, when a large grain polycrystalline silicon is used, the arsenic ion is likely to cause channeling at the time of ion implantation of the arsenic for doping in the source/drain of NMOS and the gate electrode.
Consequently, it was discovered that the arsenic ion, which must remain in the gate electrode, reaches the surface of the silicon substrate and causes anomalies in the electric characteristics of the transistor.
In order to solve the above problem, H. Ito proposes a gate structure which is formed by double layers of the large grain polycrystalline silicon.
This gate structure is formed by inserting an electrically non-conductive oxide layer between two polycrystalline silicon layers such that the face orientation of the upper layer made of large grain polycrystalline silicon is not affected by the face orientation of the lower layer of large grain polycrystalline silicon.
The above structure including the oxide layer reduces the probability of channeling by the arsenic ion, because the face orientations of the upper and lower large grain polycrystalline silicon layers slip to each other.
Furthermore, by addition of an N-type phosphorous impurity at the concentration of 3.times.10.sup.19 cm.sup.-3 to those large grain polycrystalline silicon layers, a successful result is obtained in preventing depletion of the NMOS electrode, if the thermal treatment is performed within a temperature range in which the boron in the NMOS electrode does not pass through. As a result of this structure, two problems in the case of the dual gate structure can be settled.
A method is described below for manufacturing the dual gate CMOS proposed by H. Ito et al., which uses two layers of phosphorous doped large grain polycrystalline silicon by placing one upon another.
As shown in FIG. 6A, element separating regions 2 are formed on a silicon substrate 1, a P well 3 and an NMOS channel region 4 are formed in the NMOS forming region, and an N well 5 and a PMOS channel region 6 are formed in the PMOS forming region.
After growing the gate oxide film 7, a first phosphorous doped amorphous silicon layer 8 is grown, and on that layer, an oxide layer 9 having a thickness of 1 .mu.m is continuously grown by the use of a mixed gas of oxygen and nitrogen, and a second phosphorous doped amorphous silicon layer 10 is formed on the oxide layer 9. Here, the first and second phosphorous doped amorphous silicone layers 8 and 10 contain phosphorous at a concentration of 3.times.10.sup.19 cm.sup.-3.
Subsequently, as shown in FIG. 6B, a heat treatment is conducted (at 900.degree. C. for 10 seconds) for crystallization of the first and the second phosphorous doped amorphous silicon layers 8 and 10, and a first phosphorous-doped large grain polysilicon layer 11 and a second phosphorous doped large grain polysilicon layer 12 are formed.
Subsequently, as shown in FIG. 6C, the NMOS gate electrode 13 and the PMOS gate electrode 14 are formed by patterning the first and second phosphorous-doped large grain polysilicon layers 11 and 12.
Next, an N-type LDD region 15 is formed by implanting phosphorous or arsenic in the NMOS Channel region 4 and a P-type LDD region 16 is formed by implanting boron or BF.sub.2 in the PMOS Channel region 6.
As shown in FIG. 6D, after forming the side wall spacer 17, arsenic is implanted in the NMOS region to dope source/drain region 18 and the NMOS gate electrode into N.sup.+.
Similarly, boron or BF.sub.2 is implanted in the PMOS region to dope the source/drain region and PMOS gate electrode with P.sup.+. At this time, the PMOS gate electrode 14 becomes P.sup.+ by compensation of N-type dopants.
Next, as shown in FIG. 6E, the device is heat treated (at 1020.degree. C. for 40 seconds) for activation.
As shown in FIG. 6F, silicide layers 20 are formed on the surfaces of the N.sup.+ type source/drain region and NMOS gate electrode, and on the surfaces of the P.sup.+ type source/drain region and the PMOS gate electrode in order to reduce the layer resistance.
The method of manufacturing the semiconductor device shown in FIG. 6 uses a gate electrode structure which is formed by double layers of phosphorous doped large grain polysilicon and the phosphorous at a concentration of 3.times.10.sup.19 cm.sup.-3 is contained as an impurity in the P.sup.+ type PMOS electrode 14.
This impurity is introduced for preventing the depletion of the NMOS electrode 13, and the impurity of phosphorous in the PMOS electrode 14 is not substantially necessary. The N-type impurity of phosphorous is compensated by a P-type impurity of boron in the source/drain region 19 and the gate electrode 14 of the PMOS.
However, there is a problem that the layer resistance of the PMOS gate rises due to the presence of the phosphorous.
When the silicide layer is formed on the gate electrode surface, another problem arises that the contact resistance between the silicide layer and the large grain polysilicon forming the P.sup.+ type gate electrode 14 rises.
Furthermore, since the upper and lower layers of large grain polysilicon have the same grain size, and if the upper layer and the lower layer are formed such that both layers have the same face orientation by chance, a problem arises that channeling of arsenic is caused.
It is therefore an object of the present invention to provide a semiconductor device and a method of producing the same in which the above problems are solved.